[quote name=\'SHMUELD\' post=\'420065\' date=\'Jan 27 2008, 09:46 AM\']I am new to PCI Express. Could someone please explain to me how slow back end applications should interface to the PCI Express bus. We have bought a PLDA core that appears to do writes to the backend logic in Burst mode @125MHz. At the same time it expects the read cycle from the back end logic to be taken care of with a DMA access ! What is the best way to manage these types of accesses ? We need to interface this bus to a Dual Port Ram that runs at 20 Mhz.
How do other applications handle this type of speed ? Do all applications that interface to the PCI Express bus use DMA and Burst mode types of accesses ?
Is there anyway to forces the PCI Express accesses to do single address accesses ? (Yes I know this will slow things down a lot !?) Or is the nature of PCI Express only ever to do high bandwidth accesses which can only be implemented through DMA and burst modes ?[/quote]
Technically, PCI Express is not a bus. A bus is a data path where you can attach several devices at the same time, sharing this data path. PCI Express is a point-to-point connection, i.e. it connects only two devices and no other device can share this connection. Just to clarify, on a motherboard using standard PCI slots, all PCI slots are connected to the PCI bus and share the same data path. On a motherboard with PCI Express slots, each PCI Express slot is connected to the motherboard chipset using a dedicated lane, not sharing this lane (data path) with other PCI Express slots. In name of simplification, we are calling PCI Express as a "bus", since for laymen “bus†is easily recognized as “data path between devicesâ€.
